1. Field of the Invention
The invention relates to a semiconductor package and a fabricating method thereof.
2. Description of the Related Art
Recently, portable electronic devices such as a mobile phone, a PMP and others have been required to achieve high-functionality, miniaturization, light-weight and price reduction. According to the tendency, a semiconductor package mounted in portable electronic devices has been also developed in a type of a 3D semiconductor package to be more innovative and price-competitive. The 3D-semiconductor package has been used by a semiconductor stacking technology using a through silicon via (TSV). The semiconductor stacking technology using the TSV is a technology indicating that semiconductor dies or semiconductor packages are perpendicularly stacked. The semiconductor stacking technology leads to reduction of the length between the semiconductor die and the semiconductor package, and thus achieves high-functionality and miniaturization of semiconductor packages.
Now, the semiconductor package provided with the through silicon via is fabricated in a thin wafer level. The through silicon via is formed by filling through holes formed on a wafer with conductive materials. The through holes are formed by using a laser drilling method or a deep reactive ion etching (DRIE) method.
However, the laser drilling method performs laser drilling in proportion to the number of through holes and leads to long time for fabrication and high cost. Additionally, the laser drilling method also leads to formation of a through hole in an inaccurate position, because it is difficult for the laser drilling method to accurately form the through hole in a desired position. Side wall bowing, silicon debris or the like are caused by the laser drilling method when a through hole is formed on a wafer, resulting in generating defects of the through silicon via formed in an inner portion of the through hole afterwards. Accordingly, the laser drilling method results in the reduction of yield of semiconductor packages.
Further, a deep reactive ion etching (DRIE) method leads to slope angle indicating that a side wall of the through hole is sloped, side wall roughness indicating that the side wall becomes rough and step coverage indicating that the side wall of the through hole is stepped, resulting in generating defects of the through silicon via formed on the through hole afterwards. Accordingly, the DRIE method also results in the reduction of yield of semiconductor packages.
The present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.